The present invention relates to a semiconductor device using a III-V nitride semiconductor and a method for manufacturing the semiconductor device. More specifically, the present invention relates to a semiconductor device having a Schottky electrode formed on a semiconductor layer consisting of a III-V nitride semiconductor, and a method for manufacturing the semiconductor device.
Conventionally, a III-V nitride semiconductor such as gallium nitride (GaN) has been widely used as a material for an active layer of an optical device since it has a direct transition energy band structure and a wide band gap. Recently, since the III-V nitride semiconductor is characteristically high in breakdown field intensity and high in electron saturation velocity, use of this III-V nitride semiconductor to a high frequency and high power electron device has been considered.
Among electron devices using the nitride semiconductor, development of a heterojunction field effect transistor (hereinafter, “HFET”), in particular has been considered.
Examples of the HFET device using the III-V nitride semiconductor include an HFET device constituted so that a GaN layer and an aluminum gallium nitride (AlGaN) layer are formed on a semi-insulating substrate by epitaxial growth, and so that a gate electrode that is a Schottky electrode and a source electrode and a drain electrode that are ohmic electrodes are provided on the AlGaN layer. In this HFET device, a two-dimensional electron gas layer (hereinafter, “2DEG layer”) is formed near an interface of the GaN layer with the AlGaN layer and the 2DEG layer is employed as a high electron mobility channel region.
Nevertheless, because of presence of a high density trap level on a surface of the III-V nitride semiconductor, carries are captured and emitted in traps on the surface of the AlGaN layer, with the result that a phenomenon of deterioration in high frequency characteristics or so-called frequency dispersion occurs.
To suppress this frequency dispersion, there are known a method for reducing a trap density on the surface of the AlGaN layer by covering a region between the gate electrode and the source electrode and a region between the gate electrode and the drain electrode on the surface of the AlGaN layer with a surface protection film consisting of silicon nitride (SiN), and a method for providing a surface protection film consisting of a low concentration n type GaN on the AlGaN layer, and forming the gate electrode interposing the surface protection film (see, for example, Japanese Patent Application Laid-Open No. 2002-359256).
If the surface protection film consisting of SiN is used, the trap density on the surface of the AlGaN layer can be reduced in lateral portions of the gate electrode. However, in a fringe region that is a lower side end of the gate electrode, surface charge influences the channel region, with the result that the frequency dispersion cannot be sufficiently suppressed. If the surface protection film consisting of low concentration n type GaN is used, a distance between the gate electrode and the channel region is increased by a thickness of the surface protection film, with the result that a mutual conductance (gm) of the HFET device is reduced.
Meanwhile, as the HFET device using a gallium arsenide (GaAs) based material, there is known an HFET device having a so-called spike-gate structure in which a convex portion having a V-shaped cross section is provided in a lower portion of the gate electrode so as to decrease the influence of the surface traps (see, for example, Japanese Patent Application Laid-Open No. 2001-102354, and H. Furukawa and six others, “High power-added efficiency and low distortion GaAs power FET employing spike-gate structure”, Solid-State Electronics, Elsevier Science Ltd., 1997, Volume 41, No. 10, pp. 1599-1604).
FIG. 10 is a cross-sectional block diagram that depicts a conventional GaAs based HFET device including the spike-gate. As shown in FIG. 10, an n type GaAs layer 102 and high concentration n type GaAs layer 103 are formed on a substrate 101 in this order. A concave portion 102a having a V-shaped cross section is provided in an upper portion of the n type GaAs layer 102, and the high concentration n type GaAs layer 103 is formed into a recess so as to open the concave portion 102a and surroundings of the concave portion 102a. In the region formed in the recess of the high concentration n type GaAs layer 103 on the n type GaAs layer 102, a gate electrode 104 is provided to be filled into the concave portion 102a. In addition, a source electrode 105 and a drain electrode 106 are provided on the high concentration n type GaAs layer 103.
In the HFET device shown in FIG. 10, since the gate electrode 104 is provided to be filled into the concave portion 102a, a convex portion having a V-shaped cross section is provided on a bottom side of the gate electrode 104 (that is, on a bottom of the concave portion 102a). A depth of the concave portion 102a is set so that the convex portion provided on the bottom side of the gate electrode 104 substantially functions as a gate.
By doing so, as compared with an ordinary recess structure, a gap between an upper surface of the n type GaAs layer 102 and the channel region can be set wide. It is, therefore, possible to decrease the influence of the traps on the upper surface of the n type GaAs layer 102 on the channel region, and suppress the frequency dispersion resulting from the traps on the surface of the n type GaAs layer 102.
In order to form the gate electrode 104 having such a structure, the concave portion 102a is formed using an anisotropic etchant having different etch rates according to plane orientations. Specifically, the concave portion 102a inclined at about 54.7 degrees with respect to the upper surface of the n type GaAs layer 102 is formed by wet etching using an etchant having an etch rate on a (100) plane of GaAs higher than an etch rate on a (111) plane. The concave portion 102a is formed into a recess in a [100] direction of the crystal plane, having a (111) plane of GaAs as an inclined surface, and having a V-shaped cross section.
However, if the spike-gate structure of the conventional GaAs based HFET device is applied to the HFET device using the III-V nitride semiconductor, it is difficult to form a minute concave portion in the upper portion of the III-V nitride semiconductor layer. This is because crystals of the III-V nitride semiconductor are chemically stable and no orientation dependent anisotropic wet etching appropriate for this HFET device is present.
As can be seen, the HFET device using the III-V nitride semiconductor has the following disadvantages. Since it is difficult to form the gate electrode having the concave portion on the bottom side of the spike-gate or the like, the influence of the traps on the upper surface of the III-V nitride semiconductor layer on the channel region cannot be sufficiently decreased. Hence, the frequency dispersion inhibits obtaining good high frequency characteristics.